已获得的专利 

1． 向东，孙家广，降低非扫描可测试性设计管脚开销的方法，国家发明专利，专利号：ZL 02 1 46776.5, 2004.12。 

2． D. Xiang, J. Sun, M. Chen, and S. Gu, Cost-Effective Scan Architecture and a Test Application Scheme, US Patent US 6,959,426 B2, Oct. 25, 2005. 

3． D. Xiang, J. Sun, and K. Li, A New Test Point Architecture for High-Quality Testability Design, US Patent,US 7,051,302 B2 , May 23, 2006. 

4． 向东，孙家广,李开伟, 基于扫描森林的扫描测试方法, 国家发明专利，ZL02159931.9， (2006.8)。 

5． 向东，孙家广,李开伟, 构造无故障屏蔽奇偶测试的扫描链和扫描森林的方法, 国家发明专利，ZL 200410009678.2 (申请时间：2004.10.15，授权日期：2006.10.4)。 

6． 向东，孙家广，陈明静，采用加权扫描选通信号的扫描自测试结构，ZL2005100113820.9， 2008.6.18。 

7． 向东，孙家广,李开伟, 构造具有低测试功耗的两级扫描结构，ZL200410088881.3, 2008.6。 

8． D. Xiang, J. Sun, and M. Chen, Scan-based self-test structure and method using weighted scan enable signals，US Patent, US7,526,696 B2, Apr. 2009. 

9． 向东，李开伟，路径延迟故障测试压缩及装置，国家发明专利，ZL200810056676.7, 2010.1.20. 

10. 向东,赵阳, 一种路径延迟故障模拟方法及装置,专利号: ZL200810057433.5, 2010.9. 

11. 向东,赵阳, 一种确定自测试数据压缩及装置, ZL2008 1 0057431.6, 2010.9. 

12. 向东,王琦,陈振, 二维torus网络中无死锁自适应路由方法, ZL2008 1 0104406.9,2010.9.1. 

13. 向东，陈振，王琦，三维torus 网络无死锁自适应路由算法，ZL 2008 1 0104405.1， 2011.5.11。 

14. 向东,罗伟, Torus网络中无死锁自适应路由算法, ZL 2011 1 0144882.5, 2013.7.10. 

15. 向东,陈振, 延迟测试的测试向量集生成方法, ZL 2011 0216891.0, 2013.6.19. 申请了10余项国家发明专利。 

主要研究项目

1． 降低测试复杂性的DFT技术，国家自然科学基金青年基金，（负责人，1994.1-1995.12）。 

2． 提高测试码产生效率的DFT技术，国家自然科学基金，（负责人，1999.1-2001.12）。 

3． 采用新的扫描链构造技术提高BIST的测试效率，国家自然科学基金（负责人，2004.1-2006.12）。 

4． 数字系统可测试性设计理论研究， 国家杰出青年基金（负责人，2005.1- 2008.12）。 

5． 基于路由技术多计算机网络的容错组播及广播, 国家自然科学基金（负责人，2006.1-2008.12）。 

6． Mesh/Torus网络高性能,无死锁,低功耗路由协议，清华大学，信息学院重点基础研究基金（负责人，2007.6-2008.12）。 

7． 片上网络高性能低功耗路由器设计，国家863高技术探索导向类 （负责人，2009.1- 2010-12）。 

8． 数字VLSI延迟故障测试码产生，故障模拟，测试数据压缩，及低功耗测试，国家自然科学基金重大国际合作项目（负责人，2010.1- 2012-12）。 

9． 数字系统小延迟缺陷诊断及测试--理论与方法，(负责人,2012.1-2015.12),国家自然科学基金。 

10． 高性能高可靠性片上网络设计，国家教育部自主研究计划交叉基金， (负责人，2012.1-2014.12)。 

11． 大型复杂的多核/众核系统低成本测试及可测试性设计, (负责人,2014.1-2017.12),国家自然科学基金。 

有代表性的论著 

非扫描可测试性设计： 

[1] D. Xiang, Y. Xu, and H. Fujiwara, “Non-scan design for testability for synchronous sequential circuits based on conflict resolution,” IEEE Trans. On Computers, vol. 52, no. 8, pp. 1063-1075, 2003. 

[2] D. Xiang and H. Fujiwara, “Handling the pin overhead problem for high quality and at-speed test,” IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems, vol. 21, no. 9, pp. 1105-1113, 2002. 

[3] D. Xiang and Y. Xu, “Cost-effective non-scan design for testability for synchronous sequential circuits,” Proc. of 19th  IEEE Int. Conference on Computer Design, pp.154-159 , Austin, USA, Sept, 2001. 

[4] D. Xiang and Y. Xu, “Partial reset for synchronous sequential circuits using almost independent reset signals,” Proc. of 19th  IEEE VLSI Test Symposium, pp.82-87, Los Angels, April, 2001. 

[5] D. Xiang, S. Gu, and H. Fujiwara, “Non-scan design for testability based on fault-oriented conflict analysis,”  Proc. of  11th  IEEE Asian Test Symposium, Guam, USA, Nov., 2002. 

[6] D. Xiang, S. Gu, and H. Fujiwara, “Non-scan design for testability for  mixed RTL circuits with both data paths and controller via conflict analysis,” Proc. of 12th IEEE Asian Test Symposium, pp. 300-303, 2003. 

[7] D. Xiang, S. Gu, and H. Fujiwara, “Non-scan design for testability for synchronous sequential circuits based on fault-oriented conflict analysis,” IEICE Trans. on Information and Systems, vol.E86-D, pp. 2407-2417, Nov., 2003. 

[8] D. Xiang, S. Gu, and Y. Xu, “Non-scan DFT based on hard fault oriented  conflict analysis,”  Journal of Tsinghua University, pp.1001-1004, vol. 43, no. 7, 2003 (in Chinese). 

[9] D. Xiang, S. Gu, and Y. Xu,  “Partial reset for synchronous sequential circuits using independent reset signals,” Chinese Journal of Computers,  vol. 27, no. 2, pp. 224-230, 2004 (in Chinese). 低成本扫描测试： 

[10] D. Xiang, S. Gu, J. Sun, and D. Wu, “Cost-effective scan design with non-scan test application cost and test power,” in Proc. of ACM/IEEE Design Automation Conference, pp. 744-747, June, Anaheim, 2003. 

[11] D. Xiang, K. Li, and H. Fujiwara, “Design for scan testing with low test application cost and low test data volume by reconstructing scan flip-flops,”  in Proc. of 14th IEEE Asian Test Symposium, pp. 318-321, Dec., 2005. 

[12] D. Xiang, K. Li, and H. Fujiwara, “Localizing test power consumption for scan testing,” in Proc. of 6th IEEE Int. Workshop on RTL and High Level Testing, pp. 18-23, 2005. 

[13] D. Xiang and K. Li, “Low power scan testing using a two-stage scan architecture,”  Chinese Journal of Computers, pp. 786-791, no. 5, 2006 (in Chinese). 

[14] K. Li and D. Xiang, “Scan testing with low power, test application time and reduced test data volume,” Journal of Tsinghua University, pp. 98-101, no. 1, 2006(in Chinese). 

[15] D. Xiang, K. Li, J. Sun, and H. Fujiwara, “Reconfigured scan forest for test application cost, test data volume and test power reduction,” IEEE Trans. on Computers, vol. 56, no. 4, pp. 557-562, April 2007. 

[16] D. Xiang, K. Li, H. Fujiwara, K. Thulasiraman, and J. Sun, “Constraining transition propagation for low power scan testing using a two-stage scan architecture,”  IEEE Trans. Circuits and Systems-II, vol. 54, no. 5, pp. 450-454, May 2007. 

[17] D. Hu and D. Xiang, “Test power reduction using clock disabling,” Journal of Tsinghua University, vol. 47, no. 7, pp. 1216-1219, July 2007 (in Chinese). 

[18] Q. Xu, D. Hu, and D. Xiang, “Pattern-directed circuit partitioning for test power reduction,” in Proc. of IEEE Int. Test Conference, Santa Clara, Oct. 2007. 

[19] Z. Chen, D. Xiang, and B. Yin, “A power-effective scan architecture using scan flip-flops clustering and post-generation filling,” in Proc. 19th  ACM Great Lakes Int. Symp. on VLSI,  pp. 517-522, May 2009. 

[20] D. Xiang, D. Hu, Q. Xu, and A. Orailoglu, “Low-power scan testing for test data compression using a routing-driven scan architecture,” IEEE Trans. on Computer-Aided Design, vol. 28, pp. 1101-1105, July 2009. 

[21] Z. Chen, S. Seth, D. Xiang, and B. Bhattacharya,“A unified solution to scan test volume, time and power minimization,”in Proc. of 23th IEEE/ACM VLSI Design Conference, Jan. 2010. 

[22] Z. Chen, S. Seth, D. Xiang, and Bhargab B Bhattacharya, “ PVT: Unified reduction of test power, volume, and test time using double-tree scan architecture ,” Journal of Low Power Electronics, American Scientific Publishers,   July 2010. 

[23] J. Li, Y. Huang, and D. Xiang, “Prediction of compression bound and optimization architecture of linear decompression-based schemes,”  in Proc. of 29th IEEE VLSI Test Symposium, May 2011. 

[24] Z. Chen, D. Xiang, J. Li, and Y. Huang, “Virtual circuit model for low-power scan testing in linear decompressor-based compression environment,” IEEE North Atlantic Test Workshop, 2011. 

[25]D. Xiang and Z. Chen, “Selective test response collection for low-power scan testing with well-compressed test data,”  in Proc. of 20th IEEE Asian Test Symposium, pp. 40-45, Nov. 2011. 

[26] Z. Chen, S. Seth, D. Xiang, and B. Bhattatcharya, “Diagnosis of multiple scan-chain faults in the presence of system logic defects,”  in Proc. of 20th IEEE Asian Test Symposium, Nov. 2011. 

[27] Zhen Chen, Jia Li, Dong Xiang and Yu Huang, “Virtual circuit model for low power scan testing in linear decompressor-based compression environment,”   in Proc. of 20th IEEE Asian Test Symposium, pp. 96-101, Nov. 2011. 

部分扫描设计 

[28] D. Xiang and J.H.Patel, “Partial scan design based on valid state information and functional information,” IEEE Trans. on Computers, vol.53, no.3, pp.276-287, 2004. [29] D. Xiang and Y. Xu, “A multiple phase partial scan design method,” Proc. of 10th IEEE Asian Test Symposium, Kyoto, pp.17-22, Nov., 2001. 

[30] D. Xiang and J. Patel, “A global algorithm for the partial scan design problem using circuit state information,” Proc. of IEEE Int. Test Conference, pp. 548-557,Nov., 1996. 

[31] D. Xiang and X. Liu,  “Partial scan design based on conflict analysis and circuit state information,”  Journal of Electronics,  vol. 26, no.1, pp. 124-130, 2004 (in Chinese). 

自测试 

[32] D. Xiang, M. J. Chen, J. G. Sun, and H. Fujiwara, “Improving the effectiveness of scan-based BIST using scan chain partitioning,” IEEE Trans. on Computer-Aided Design, vol. 24, no. 6, pp.916-927, 2005. 

[33] D. Xiang, M. J. Chen, J. Sun, and H. Fujiwara, “Improving test quality of scan-based BIST by scan chain partitioning,” Proc. of 12th IEEE Asian Test Symposium, pp.12-17, 2003. 

[34] D. Xiang, M. Chen, K. Li, and D. Wu, “Scan-based BIST using an improved scan forest architecture,”  in Proc. of  13th IEEE Asian Test Symposium, pp. 88-93, Nov., 2004. 

[35] D. Xiang, D. Z. Wei, and S. S. Chen, “A global test point placement algorithm for combinational circuits,” Proc. of 5th IEEE Int. Conf. on VLSI Design, pp. 227-232, 1992. 

[36] D. Xiang and D. Z. Wei, “Global: A design for random testability algorithm,” J. of Computer Science and Technology, vol. 9, no. 2, pp. 182-192, 1994. 

[37] D. Xiang, D. Z. Wei, and S. S. Chen, “Probabilistic models for estimation of random and pseudorandom test length,” J. of Computer Science and Technology, vol. 7, no.2, pp. 164-174, 1992. 

[38] D. Xiang,“Knowledge-based design for testability,”Acta Electronica Sinica, vol. 19, no. 3,pp. 106-109, 1991 (in Chinese). 

[39] D. Xiang, M. Chen, and H. Fujiwara, “Using weighted scan enable signals to improve test effectiveness of scan-based BIST,”  in  Proc. 14th IEEE Asian Test Symposium, pp. 126-131, Dec., 2005. 

[40] D. Xiang, Y. Zhao, K. Chakrabarty, J. Sun, and H. Fujiwara, “Compressing test data for deterministic BIST using a reconfigurable scan architecture,” in  Proc. of 15th IEEE Asian Test Symposium, Japan, pp.299-304, Nov., 2006. 

[41] D. Xiang, M. Chen, and J. Sun, “Using weighted scan enable signals to improve the test effectiveness of scan-based BIST,” Science in China, vol. 36, no. 8, pp. 902-911, 2006 (in Chinese). 

[42] D. Xiang, M. J. Chen, and H. Fujiwara,“Using weighted scan enable signals to improve test effectiveness of scan-based BIST,” IEEE Trans. On  Computers, vol. 56, no. 12, pp. 1619-1628, 2007 (featured article). 

[43] D. Xiang, Y. Zhao, K. Chakrabarty, and H. Fujiwara, “A reconfigurable scan architecture with weighted scan enable signals for deterministic BIST,”IEEE Trans. on Computer-Aided Design, vol. 25, no. 6, pp. 999-1012, June, 2008. 

[44] D. Xiang, M. Chen, and J. Sun, “Scan BIST with biased scan test signals,” Science in China (English version), vol. 51, no. 7, pp. 881-895, July 2008. 

可测试性分析 

[45] D. Xiang, Y. Xu, and H. Fujiwara, “Non-scan design for testability for synchronous sequential circuits based on conflict analysis,” Proc. of IEEE Int. Test Conference, Atlantic City, pp. 420-429, Oct., 2000. 

[46] D. Xiang, S. Venkataraman, K. Fuchs, and J. Patel, “Partial scan design based on circuit state information,” in Proc. 33th of ACM/IEEE Design Automation Conference, pp. 807-8l2, Las Vegas, l996. 

[47] D. Xiang, “SCTM: A conflict oriented testability measure,” Chinese Journal of Computers, vol. 16,  no. 4, pp. 273-280, 1993 (in Chinese). 

[48] D. Xiang and D. Z. Wei,  “On functional circuit testability analysis,”  Chinese Journal of Computers,  vol. 16, no. 1, pp. 35-44, 1993 (in Chinese). 

[49] D. Xiang and K. Thulasiraman, “Design for testability of path delay faults based on conflict analysis,”in Proc. of IEEE DFT/BIST Workshop, USA, 1995. 

[50] D. Xiang and D. Z. Wei, “Testability estimation for hierarchical description circuits,” Proc. of IEEE Pacific Rim Fault-Tolerant Systems Symposium, 1993. 

延迟测试 

[51] D. Xiang, K. Li, H. Fujiwara, and J. Sun, “Generating compact robust and non-robust tests for complete coverage of path delay faults based on stuck-at tests,” in Proc. of 24th IEEE Int. Conference on Computer Design, pp. 446-451, 2006. 

[52] D. Xiang, Y. Zhao, K. Li, and H. Fujiwara, “Fast and effective fault simulation for path delay faults based on selected testable paths,” in Proc. of IEEE Int. Test Conference, Santa Clara, pp. 707-716, Oct. 2007. 

[53] D. Xiang, K. Chakrabarty, D. Hu, and H. Fujiwara, “Scan testing for complete coverage of path delay faults with reduced test data volume, test application time and hardware,” in Proc. of 16th IEEE Asian Test Symposium, Oct. 2007. 

[54] B. Yin, D. Xiang, and Z. Chen,“New techniques for accelerating small delay ATPG and generating compact test sets,” in Proc. of 22th IEEE/ACM Int. Conf. on VLSI Design, Jan. 2009. 

[55] Z. Chen, B. Yin, and D. Xiang, “Conflict-driven scan architecture for high transition fault coverage and low power,”  in the Proc. of 14th IEEE/ACM Asian and South Pacific Design Automation Conference, Jan. 2009. 

[56] D. Xiang, B. Yin, and K. T. Cheng, “Dynamic test compaction for transition faults in broadside scan testing based on an influence cone measure,“ in the Proc. of 27th IEEE VLSI Test Symposium, pp. 251-256, May 2009. 

[57] Z. Chen, D. Xiang, and B. Yin, “A novel test application scheme for high transition fault coverage and low test cost,” in Proc. of 27th IEEE VLSI Test Symposium, pp. 146-151, May 2009. 

[58] D. Xiang, B. Yin, and K. Chakrabarty, “Compact test generation for small delay defects using testable path information,”  in 18th  Proc. of Asian Test Symposium, Nov. 2009. 

[59] Z. Chen and D. Xiang, “Low-capture-power at-speed testing using partial launch-on-capture Test Scheme,” in Proc. of 28th IEEE VLSI Test Symposium, May 2010. 

[60] Z. Chen, S. Seth, and D. Xiang, “A novel hybrid delay testing scheme with low test power, volume, and time,” in Proc. of 28th IEEE VLSI Test Symposium, May 2010. 

[61] D. Xiang and Z. Chen, “Compact test generation for complete coverage of path delay faults in a standard scanned circuit,”in Proc. of Int. Workshop on Register-Transfer Level Testing, pp. 67-75, Dec. 2009. 

[62] Z. Chen and D. Xiang，“A novel test application scheme for high transition fault coverage and low test cost，” IEEE Trans. on Computer-Aided Design, vol. 29, no. 6, pp. 966-976, June 2010. 

[63] Z. Chen, J. Feng, D. Xiang, and B. Yin, “Scan chain configuration based X-filling for low power and high quality testing”, IET Computers & Digital Techniques, Vol.4, No.1, pp.1–13, 2010 (Featured paper). 

[64] Z. Chen, K. Chakrabarty, and D. Xiang, “MVP: Capture-power reduction with minimum-violations partitioning for delay testing,” in Proc. of IEEE/ACM Int. Conf. on Computer-Aided Design, pp. 149-154, Nov. 2010. 

[65] J. Li, Q. Xu, and D. Xiang, “Compression-aware capture power reduction for at-speed testing,” in Proc. 16th IEEE/ACM Asia and South-Pacific Design Automation Conference, Jan. 2011. 

[66] Z. Chen, K. Chakrabarty, and D. Xiang, “MVP: Minimum-violations partitioning for reducing capture power in at-speed delay-fault testing,”  IEEE Trans. on Computer-Aided Design, vol. 30, no. 11, pp. 1762-1767, Nov. 2011. 

[67] D. Xiang, Z. Chen, and L.T. Wang, “Scan flip-flop grouping to compress test data and compact test responses for broadside delay testing,” ACM Trans. on Design Automation of Electronic Systems, vol. 17, no. 2, article 18, April 2012. 

[68] D. Xiang, J. Li, K. Chakrabarty, and X. Lin, “Test Compaction for Small Delay Defects Using an     Effective Path Selection Scheme,”  ACM Trans. on Design Automation of Electronic Systems, vol. 18, no. 3,  July 2013. 

[69] D. Xiang, W. Sui, B. Yin, and K.-T. Cheng, “Compact test generation with an influence input measure for launch-on-capture transition fault testing,” accepted to appear in IEEE Trans. on VLSI Systems, Aug. 2013. 

测试调度 

[70] D. Xiang, “A new parallel testing scheme based on test subsession partitioning,”  Acta Electronica Sinica, vo1.27, No.2, pp.28-31, 1999 (in Chinese). 

[71] D. Xiang and D. Z. Wei, “Optimized design for test scheduling,” Chinese Journal of Computers,  vol. 17, no.1, pp.37-45, 1994 (in Chinese). 

[72] D. Xiang, “Test scheduling using test subsession partitioning,” Proc. of 3th IEEE Asian Test Symposium, Japan, 1994. 

[73] D. Xiang, “Test scheduling and control in a parallel processing environment,” Proc. of 2th IEEE Asian Test Symposium, 1993. 

[74] D. Xiang and D. Z. Wei, “Optimal design for parallel testing using circuit partitioning,” Proc. of 7th IEEE Int. VLSI Design Conference, pp. 297-300, 1994, Calcutta, India. 

[75] D. Xiang, D. Z. Wei, and T. H. Chen, “An optimal design for parallel testing,” Proc. of IEEE Pacific Rim Fault-Tolerant Systems Symposium, Kawasaki, Japan, 1991. 

[76] D. Xiang and D. Z. Wei, “Dynamic test scheduling in a distributed system,” Acta Electronica Sinica,  vol. 20,  no. 6,  pp. 53-58, 1992 (in Chinese). 

[77] D. Xiang and D. Z. Wei,  “Test scheduling and its control,” Acta Electronica Sinica, vol. 21, no.11, pp.33-42, 1993 (in Chinese). 

片上网络 

[78] D. Xiang and Y. Zhang, “Cost-effective power-aware core testing in NoCs based on a new unicast-based multicast scheme,” IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems, vol. 30, no. 1, pp. 135-147, Jan. 2011. 

[79] X. Wang and D. Xiang, “Multi-mapping meshes: a new communicating fabric for Networks-on-Chip,”in Proc. of 16th IEEE Int. Conf. on Parallel and Distributed Systems, Dec. 2010. 

三维IC测试 

[80] J. Li and D. Xiang, “DfT optimization for pre-bond testing of 3D-SICs containing TSVs,” in 28th IEEE Int. Conf. on Computer Design, Oct. 2010. 

[81] D. Xiang, K. L. Shen, and Y. D. Deng, “DfT optimization for pre-bond testing of 3D-SICs containing TSVs,” in Proc. of 21th IEEE Asian Test Symposium,pp.101-106, 2012. [82] D. Xiang and K. L. Shen, “A thermal-driven test application scheme for pre-bond and post-bond scan testing of 3-dimensional ICs,”accepted to appear in ACM Journal on Emerging Technologies of Computing Systems, Jan. 2013. 

[83] Dong Xiang, Gang Liu, Krishnendu Chakrabarty and Hideo Fujiwara, “Thermal-Aware Test Scheduling for NOC-Based 3D Integrated Circuits,” accepted to appear in Proc. of 21th IFIP/IEEE Int Conference on VLSI-SOC, 2013. 

[84]D. Xiang, “A cost-effective scheme for network-on-chip router and interconnect testing,” accepted to appear in Proc. of 22th IEEE Asian Test Symposium, 2013. 

容错计算 

[85] D. Xiang, “Fault-tolerant routing in hypercube multicomputers using local safety information,” IEEE Trans. on Parallel and Distributed Systems, vol. 12, no. 9, pp. 942-951, 2001. 

[86] D. Xiang and A. Chen, “Reliable broadcasting in wormhole-routed  hypercube -connected networks using local safety information,” IEEE Trans. on Reliability, pp. 245-256, vol. 52, no. 2, June, 2003. 

[87] D. Xiang, A. Chen, and J. Wu, “Fault-tolerant broadcasting for hypercubes  based on local safety information,” Proc. of 9th IEEE Int. Conf. on Parallel and Distributed Systems,  pp. 31-36, Taiwan, Dec., 2002. 

[88] D. Xiang and J. Wu, “Reliable multicasting for hypercube multicomputers using local safety information,” Proc. of 13th  Int. Conf. on Parallel and Distributed Computing Systems, Las Vegas, Aug., pp. 529-534, 2000. 

[89] D. Xiang, A. Chen, and J. Wu, “Local-safety-information-based broadcasting in hypercube multicomputers with node and link faults,” Int. Journal of Interconnection Networks, vol. 2, no. 3, World Scientific Publishers, pp. 365-378, 2001 (invited  paper). 

[90] D. Xiang and J. Wu, “Reliable unicasting in faulty hypercubes using local safety information,” Proc. of 4th  IEEE Int. Conf. on  Algorithms and Architectures for Parallel Processing,  Hong Kong,  Dec., 2000. 

[91] D. Xiang, “Partial path set-up for fault-tolerant  routing in hypercube multicomputers,” Future Generation Computer Systems, vol. 22, pp. 812-819, Elsevier Scientific Press, Aug., 2006. 

[92] D. Xiang, A. Chen, and J. Wu,“Local-safety-information-based  fault-tolerant broadcasting in hypercubes,” J. of Inform. Sci. and Eng., vol. 19, no. 3, pp.467-478, June, 2003. 

[93] D. Xiang and A. Chen, “Fault-tolerant routing in hypercubes based on partial path set-up, ” in Proc.of 2003 IEEE Int. Workshop on PMEO-PDS03 (with IPDPS03), IEEE Computer Society Press. 

[94] 向东，陈爱，孙家广,基于平面故障块三维mesh/torus网络容错路由, 《计算机学报》,  vol. 27,  no. 5,  pp. 611-618, 2004. 

[95] D. Xiang, A. Chen, and J. G. Sun, “Fault-tolerant multicasting in hypercube multicomputers using local safety information,” Journal of Parallel and Distributed Computing, vol. 66, no. 2,  pp. 248-256, 2006. 

[96] D. Xiang, Y. Zhang, and J. Sun, “Unicast-based fault-tolerant multicasting in wormhole -routed hypercubes,” Journal of Systems Architecture, vol.54, no. 12, pp. 1164-1178, Elsevier Scientific Press, 2008. 

[97] D. Xiang, Y. Zhang, and Y. Pan, “Practical deadlock-free fault-tolerant routing in meshes based on the planar network fault model,”IEEE Trans. on Computers, vol. 58, no. 5, pp. 620-633, 2009. 

[98] D. Xiang, Y. Zhang, and Y. Xu, “A fault-tolerant routing algorithm design for on-chip optical networks,” accepted to appear in Proc. of 32th IEEE Int. Symposium on Reliable Distributed Systems, Oct. 2013. 

并行/分布式计算 

[99] D. Xiang, “Deadlock-free adaptive routing in meshes with fault-tolerance ability using channel overlapping,”IEEE Trans. on Dependable and Secure Computing, vol. 8, no. 1, pp.74-88, 2011(featured article). 

[100] D. Xiang, Y. Zhang, Y. Pan, and J. Wu, “Deadlock-free adaptive routing in meshes based on cost-effective deadlock avoidance schemes,” in 36th IEEE Int. Conference on Parallel Processing, Sept. 2007. 

[101] D. Xiang, A. Chen, and J. Sun, “Fault-tolerant routing and multicasting for hypercube multicomputers based on partial path set-up,”  Parallel Computing, Elsevier Science Press, vol.31, no. 1,  pp. 389-411, 2005. 

[102] D. Xiang, J. Sun, J. Wu, and K. Thulasiraman, “Fault-tolerant routing in meshes /tori using planarly constructed fault blocks,”  in Proc. of 34th IEEE Int Conference on Parallel Processing, pp. 577-584, Oslo, Norway, 2005. 

[103] D. Xiang and A. Chen, “Fault-tolerant routing in 2D meshes/tori using limited -global-safety information,” Proc. of 31th IEEE Int. Conf. on Parallel Processing, pp. 231-238,  Vancouver, Aug.,  2002. 

[104] 向东，张跃鲤，mesh网高效无死锁路由算法，《计算机学报》，vol. 30, no. 11, pp. 1954-1963, 2007. 

[105] Z. Li , Y. Zhao, Y. Cui, and D. Xiang, “A density adaptive routing protocol for large-scale Ad hoc networks,”in Proc. of IEEE Wireless Communications and Networking Conference,  2008. 

[106] D. Xiang, Y. Pan, Q. Wang, and Z. Chen, “Deadlock-free fully adaptive routing in 2-dimensional tori based on a new virtual network partitioning scheme,” in Proc. of 28th IEEE Int. Conference on Distributed Computing Systems, pp. 454-461, 2008. 

[107] D. Xiang, Q. Wang, and Y. Pan, “Deadlock-free adaptive routing in 2D tori with a new turn model,”in Proc. 8th IEEE Int. Conf. on Architectures and Algorithms for Parallel Processing, 2008. 

[108] D. Xiang, Q. Wang, and Y. Pan, “Deadlock-free fully adaptive routing in tori based on a new virtual network partitioning scheme,” in Proc. 37th IEEE Int. Conference on Parallel Processing, pp. 612-619, Sept. 2008. 

[109] Y. Lin and D. Xiang, “An effective congestion-aware selection function for adaptive routing in interconnection networks,” in Proc.7th IEEE  Int. Conf. on  Parallel and Distributed Computing, Applications and Technologies, pp. 156-165,  2010. 

[110] W. Luo and D. Xiang, “An efficient deadlock-free adaptive routing algorithm for torus networks,” IEEE Trans. On Parallel and Distributed Systems, vol. 23, no. 5, pp. 800-808, May 2012. 

[111] D. Xiang and J. Han, “Multiple spanning tree construction for deadlock-free adaptive routing in irregular networks,” in Proc. of 10th IEEE Int. Symp. On Parallel and Distributed Processing with Application, pp. 9-16，July 2012. 

[112] X. Wang, D. Xiang, and Z. Yu, “TM: A new and simple topology for interconnection networks,” accepted to appear in Journal of Supercomputing, Springer, 2013. 

[113] D. Xiang, Z.G. Yu, and J. Wu, “Deadlock-free fully adaptive routing in irregular networks without virtual channels,”  in Proc. of 11th IEEE Int. Symp. On Parallel and Distributed Processing with Application, July 2013.